1. Field of the Invention
The present invention relates to a heat treatment jig mounting and holding an object and a heat treatment jig set having the heat treatment jig and a jig cover mounted to the top face thereof.
2. Description of Related Art
In a manufacturing process of a semiconductor device, there is a step of jointing semiconductor components (semiconductor chip, chip capacitor and chip resistor or the like) with wiring board, jointing a pair of semiconductor devices or semiconductor components (a pair of semiconductor chips etc.) (hereinafter also referred to as a pair of semiconductor components) using jointing medium such as solder and adhesive.
One of the jointing methods is that a pair of semiconductor components or the like is mounted and held to a heat treatment jig and the pair of semiconductor components having jointing parts contacting one another is given a heat treatment by a reflow oven. FIG. 30 is a schematic explanation diagram of a semiconductor device 20 having a basic configuration including a wiring substrate 21 and chip components 22 such as a chip capacitor and chip resistance. The above jointing method is used to joint the chip components 22 to the wiring substrate 21, for example
In a manufacturing process of a semiconductor device or the like having a package-on-package configuration which is a technique for jointing a pair of semiconductor devices, flip-chip configuration which is a technique for jointing a semiconductor chip to a wiring substrate and chip-on-chip configuration which is a technique for jointing a semiconductor chip to another semiconductor chip, the above jointing method is used.
Details of the semiconductor device having a package-on-package configuration, flip-chip configuration or chip-on-chip configuration are described hereinafter in detail.
[Package-On-Package Configuration Semiconductor Device]
As a complementary technology to the technology called SoC (System on Chip) that realizes a system on one Si (silicon), a technology called SiP (System in Package) is attracting attentions, in which the technology realizes several functions including memory and CPU (Central Processing Unit) by one package implementation.
The package-on-package technology is a next generation technology in the SiP technology and it is the technology for laminating packages. FIG. 31 is a schematic explanation diagram of a semiconductor device 30 having a package-on-package configuration. As shown in FIG. 31, for the semiconductor device 30, a bottom package 31 and a top package 32 are jointed by the above jointing method. The bottom package 31 includes a bottom package side wiring substrate 33, land 34, bottom package side semiconductor chip 35, bumps 36, underfill resin 37 and solder balls 38 etc. The top package 32 includes a top package side wiring substrate 40, top package side semiconductor chip 41, chip mounting adhesive 42, bonding wire 43 and mold resin 44 etc. Advantages of the package-on-package technology are listed below as compared to the chip stack (laminated) technology, which is the mainstream of current SiP technology.
Improvement of production efficiency such as yield and ease of test and cost improvement
Easy problem analysis when a failure occurred
Higher speed and integration by enabling to implement passive components together
Applicability to many applications as commercial packages can be mounted
Improvement of design flexibility by the ability to support modular feature and shape
Jointing a semiconductor device having a package-on-package configuration can be carried out by the following method. Firstly, diced bottom package 31 is held to a heat treatment jig and the top package is mounted thereon using a mounter or the like. Then the heat treatment jig is thrown into a reflow oven to be heated. This makes the bottom package 31 and top package 32 jointed.
[Flip-Chip Bonding Configuration Semiconductor Device]
A general semiconductor device includes a semiconductor chip with a plurality of circuit devices formed on a Si substrate mounted to a wiring substrate or the like. Further, in order to fulfill requested circuit operations and functions, each circuit device is connected to one another.
For the semiconductor device having a flip-chip bonding configuration, a connection between semiconductor chip and wiring substrate is formed by directly jointing the wiring substrate and circuit face of the semiconductor chip opposing to each other. FIG. 32 is a schematic explanation diagram of a semiconductor device 50 having the flip-chip bonding configuration. As shown in FIG. 32, the semiconductor device 50 includes a wiring substrate 53, land 54, semiconductor chip 55, solder bumps 56, underfill resin 57 and solder balls 58 etc. In the flip-chip bonding technology, a conducting distance to a wiring substrate is shorter than the wire bonding technology using thin metallic lines. Thus the flip-chip bonding technology has advantages such that it is excellent in high-speed transmission.
For the semiconductor device 50 having a flip-chip bonding configuration, there are solder bumps 56 using gold stud bumps formed by gold wire and solder bumps 56 using solder bumps to pads of the semiconductor chip 55. Further, solder is sometimes pre-coated to pads of the wiring substrate 53.
[Chip-On-chip Configuration Semiconductor Device]
Chip-on technology is a technology for jointing circuit faces of a pair of semiconductor chips opposing to each other using the flip-chip bonding technology. Chip-on-chip configuration semiconductor device has advantages such as a signal can be communicated at high-speed between semiconductor chips.
FIG. 33 is a schematic explanation diagram of a semiconductor device 60 having a chip-on-chip configuration. As shown in FIG. 33, the semiconductor device 60 includes a wiring substrate 63, lands 64, first semiconductor chip 65, bumps 66, underfill resin 67, solder balls 68, second semiconductor chip 71, chip mounting adhesive 72, bonding wire 73 and mold resin 74 or the like. To joint a semiconductor device having a chip-on-chip configuration, diced first semiconductor chip 65 or wiring substrate 63 having diced first semiconductor chip 65 mounted thereto is inserted to a heat treatment jig (not shown) and fixed. Then the second semiconductor chip 71 having bumps 66 formed to the circuit face is mounted thereon by a mounter (not shown) or the like. After that, by throwing the heat treatment jig into a reflow oven to be heated, the semiconductor chips are jointed.
A joint process using the heat treatment jig is carried out in manufacturing various semiconductor devices as set forth above.
A transfer jig having a push-back configuration in which a semiconductor device is held by a through-hole is disclosed in Japanese Unexamined Patent Application Publication No. 10-284639. Japanese Unexamined Patent Application Publication No. 10-284639 also discloses that a slit is formed around the through-hole.
The transfer jig disclosed in Japanese Unexamined Patent Application Publication No. 10-284639 has a push-back configuration, where lateral surface of the semiconductor device is held by inner surface of the through-hole provided to the transfer jig. However as the transfer jig and semiconductor device is made from different material, the coefficient of thermal expansion also differs.
Thus, when performing a reflow process on a semiconductor device using the transfer jig disclosed in Japanese Unexamined Patent Application Publication No. 10-284639, stress is generated to the semiconductor device from the transfer jig or problems can easily occur such as the semiconductor device falls from the transfer jig.
Incidentally, Japanese Unexamined Patent Application Publication No. 2000-228566 discloses an assembled print wiring board having a configuration in which a plurality of circuit patterns to be semiconductors are arranged and formed on a print wiring substrate. Japanese Unexamined Patent Application Publication No. 2000-228566 further discloses that a dummy pattern for additional strength is formed outside the array of circuit patterns on the assembled print wiring board and a slit is formed between the dummy pattern and circuit patterns.
A circuit device in which circuit components are mounted to a circuit board is disclosed in Japanese Unexamined Patent Application Publication No. 11-040901. Japanese Unexamined Patent Application Publication No. 11-040901 further discloses that a slit is formed around the circuit component on the circuit board so as to restrict heat conduction from the heating circuit components to the circuit board. However in Japanese Unexamined Patent Application Publication No. 2000-228566 and No. 11-040901, a jig for holding a semiconductor device is not disclosed.
A heat treatment jig for holding an object such as semiconductor device is made from metal etc. resistant to the temperature for reflow. Thus the heat capacity of the heat treatment jig itself cannot be ignored. When performing a reflow process with an object such as semiconductor device being held to a jig, heat capacity of the jig affects the object. Thus, at a reflow process, thermal history variation (variation in reflow profile) depending on outside or central parts of the object is created. Further, when simultaneously processing a plurality of objects, reflow profile differs depending on the position to insert the objects mounted in a jig.
In order to improve the reliability of object such as semiconductor device or the like, it is preferable to set a reflow temperature as low as possible in a temperature area in which a joint member such as solder melts. However a large variation in temperatures of the objects as above, the temperature must be set in consideration of the part in which the temperature is hard to increase at a reflow, so as to avoid a problem in jointing caused by solder not melted. Thus the setting temperature must be set relatively high.
However if the setting temperature is set to high, the temperature may increase too high in the position where the temperature is apt to increase at a reflow. In such case, warping or the like is generated due to a difference in coefficient of thermal expansion of materials and it causes various problems in assembility and reliability.